A 72 dB DR, CT Delta Sigma Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

Erstveröffentlichung

2014

Authors

Kauffman, John G.

Witte, Pascal

Lehmann, Matthias

Becker, Joachim

Manoli, Yiannos

et al.

Wissenschaftlicher Artikel

Published in

IEEE Journal of Solid-State Circuits ; 49 (2014), 2. - S. 392-404. - ISSN 0018-9200. - eISSN 1558-173X

Link to publication

https://dx.doi.org/10.1109/JSSC.2013.2289887

Faculties

Fakultät für Ingenieurwissenschaften, Informatik und Psychologie

Institutions

Institut für Mikroelektronik

Subject headings

[Free subject headings]: ADC | continuous time | DAC linearization | Delta Sigma modulator | low power | excess-loop-delay | dynamic-range | bandwidth | converters | noise | cmos | mw | compensation | resolution
[DDC subject group]: DDC 620 / Engineering & allied operations

Metadata

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