PLL based fully-integrated LO generation for wideband RF front-ends

Abstract

This dissertation describes Phase Locked Loop (PLL) based Local Oscillator (LO) designs for RF front-end modules targeting wideband wireless communications systems from microwave to millimeter-wave ranges. With the increase of the operating frequencies in wireless transceivers, it becomes more challenging to deliver fully integrated LO signals with high performance. In conventional single loop PLLs, the comparison frequency is restricted by the speed and noise of the phase frequency detector, which increases the in-band phase noise and the phase lock time. In this thesis, a novel dual loop PLL topology with a higher comparison frequency and a wider loop bandwidth is investigated: a frequency acquisition loop speeds up the lock time; a phase locked hold loop improves the phase noise and spurious levels. The trade-offs between the loop bandwidth, phase noise and lock time are much more relaxed than in conventional PLLs. The LO generator is fully integrated in a 0.25μm SiGe BiCMOS technology. The designs benefit from the high speed, low noise HBTs and the small sized, low power consumption CMOS transistors. The key sub circuit block designs and optimization are in detail discussed, which include phase/frequency detectors, frequency dividers and prescalers, voltage controlled oscillators, loop filter designs and so on. The loop behavior, frequency response and transient performance are studied at a system level. Three demonstrators are presented: a 35 GHz ultra-low phase noise PLL for Ka-Band radar communications which achieves state-of-the-art phase noise performance; a wideband frequency synthesizer for multi-band satellite communications with a frequency range from 16 to 24 GHz; a 3 to 5 GHz reconfigurable receiver integrated with an agile frequency synthesizer for small cell base station applications.