Bitwise ELD Compensation under Integrator Nonidealities in ∆Σ Modulators

Abstract

Quantizer (QTZ) latency and therefore excess loop delay (ELD) compensation techniques in wideband continuous-time (CT) Delta-Sigma-Modulators (DSMs) are particularly important due to stringent timing requirements. To relax timing constraints, a bitwise ELD compensation technique for internal multi-step QTZs has been introduced in prior art, which realizes feedback of individual bits in order to relax conversion time and loop filter output swings. This paper aims to analyze the impact of loop filter integrator nonidealities, most prominently finite amplifier gain-bandwidth product (GBW), when bitwise feedback is applied. The bitwise concept and possible configurations are reviewed and extended to a 3rd-order modulator. System-level simulations using Matlab/Simulink in presence of finite and varying GBW show that harmonic distortion is generated due to coefficient mismatch across the individual bits. The less bitwise feedback paths are applied, the more robust the technique becomes against these nonidealities, which makes bitwise feedback around the last integrator the most beneficial approach, while an integrator output swing reduction of −46% can be achieved compared to compensation in the QTZ.