Towards a multi-channel platform for electrochemical measurements

Abstract

Electrochemical measurements are popular non-invasive methods to investigate properties of biological samples. Especially, multi electrode array (MEA) electrochemical impedance spectroscopy (EIS) is vastly used and developed to extract detailed information from the sample under test (SUT). Thus, this work intends to develop EIS systems with small area and power consumption to allow MEA realization with small pitch. A typical potentiostatic EIS measurement system consists of a voltage excitation, a current recorder, and a processing unit. The available EIS systems mostly suffer from a bulky excitation signal source; thus, integration of a high number of electrodes is a challenging task. To overcome this issue, this work proposes an excitation signal source based on a single-bit ΣΔM DAC, whose functionality is successfully evaluated with the use of laboratory equipment. With the use of the designed PCB based singlechannel EIS, it is shown that digital multi-tone ΣΔM DAC outweighs other methods due to its unique characteristics, such as its binary valued output, small area and power consumption at the electrode site, noise immunity, spectrum engineering, and small measurement time. After a detailed comparison between the current readout SoA, it is concluded that current-mode continuous-time sigma delta modulators (C-CTΣΔM) are a better choice over resistive and capacitive transimpedance amplifiers (R-TIA, C-TIA) and time-based digitizers. The C-CTΣΔM, due to its structure, has similar noise performance as the RTIA and the C-TIA, while achieving direct digitization. It also performs better in terms of linearity, noise, input impedance, jitter sensitivity, and measurement time compared to time-based current digitizers. After an investigation between different types of DAC realizations for the C-CTΣΔM, the use of a switched capacitor resistor (SCR) DAC leads to smaller jitter and inter symbol interference (ISI) sensitivity, smaller noise, and smaller area compared to other DAC types. First, a PCB-based 24 channel MEA EIS system is designed, which only takes ≈ 20 sec to perform 24 EIS measurements (1 Hz to 100 kHz) with > 95% accuracy. Afterwards, a 3rd order SCR-DAC C-CTΣΔM is designed in CMOS technology, which occupies an area of 200×100 μm2 with 2mW power consumption and has Imin = 157 pArms and DR=95 dB in a BW=100 kHz. The designed SCR-DAC C-CTΣΔM is optimized to realize an 8×8 MEA EIS system. The reference EIS system consumes 0.5mW and occupies 120×120 μm2 per site (local excitation DAC and C-CTΣΔM), where the DAC has an area of 50×10 μm2. The ADC has Imin = 112 pArms and DR=82 dB in a BW=100 kHz.