A high speed/high linearity continuous-time delta-sigma modulator
FacultiesFakultät für Ingenieurwissenschaften, Informatik und Psychologie
InstitutionsInstitut für Mikroelektronik
Modern wireless communication systems demand wideband ADCs with high resolution and high linearity. Among different ADC topologies, CT Delta Sigma modulators are very popular due to inherent anti-aliasing filtering and relative insensitivity to circuit non-idealities. By combining the advantages of oversampling and noise shaping, CT Delta Sigma modulators enhance the SQNR performance covering a signal bandwidth from several tens of kHz up to tens of MHz. This work presents a 15MHz bandwidth, CT Delta Sigma modulator with a 70dB dynamic range designed for a high input frequency RF receiver. The high speed and high linearity requirements of such a receiver for signal above 5GHz require to employ a SiGe technology with sufficiently high transit frequency. Thus, the employed high-speed ADC must also be implemented in the same SiGe technology. To meet the target specifications of 12-bit resolution, 14-bit linearity and better than 10MHz bandwidth, a third-order single-loop CT Delta Sigma modulator with a single-bit quantizer was chosen to operate at 1.92GHz, as a reasonable compromise between sampling frequency and circuit complexity. Since the single-bit internal quantizer is inherently linear, no digital DAC linearization technique is required. All the op-amps in the modulator have been designed to feature a finite GBW of 1.5fs, and the differentiator based ELD compensation method has been extended to counteract the effect of these finite GBW. Fabricated in a 0.25um SiGe BiCMOS technology, the experimental prototype chip achieves 66.5dB SNDR and 78.1dB SFDR for a signal bandwidth of 15MHz. It dissipates 215.9mW and occupies an active area of 0.4mm^2.
Subject HeadingsModulator [GND]
Analog-to-digital converters [LCSH]
Signal processing [LCSH]
Modulators (Electronics) [LCSH]