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AuthorElkafrawy, Abdelrahmandc.contributor.author
Date of accession2016-07-20T07:02:04Zdc.date.accessioned
Available in OPARU since2016-07-20T07:02:04Zdc.date.available
Year of creation2016dc.date.created
Date of first publication2016-07-20dc.date.issued
AbstractThere is continuous research to exploit the improved speed of scaled CMOS technologies in realizing high-speed analog-to-digital converters and SAR ADCs are one of the candidates which can significantly benefit from this technology scaling. Remarkable improvements have been recently reported on single-channel time-interleaved charge-based SAR ADCs to achieve sampling rates in the range of GS/s with excellent power efficiency but the challenge of driving a large sampling capacitor with high accuracy in a short sampling window is often not addressed. Moreover, time-interleaving a large number of sub-ADCs introduces also interleaving artifacts (offset, skew) which are hard to tame at high resolutions. On the other hand, single-channel, non time-interleaved SAR ADCs suffer from settling limitations when higher resolutions together with higher conversion rates are required. In this work, a high-speed current-mode DAC is replacing the commonly used charge-mode switched capacitor DAC which alleviates the problem of driving a large input sampling capacitor in a short time. The proposed current-mode SAR ADC also uses a Gm stage which converts the input voltage to a current which is then processed in a current-based binary search algorithm SAR loop. The Gm stage is designed to achieve a 10-bit linearity over a wide differential input voltage range, which allows to choose the sampling capacitor based only on kT/C noise and not on the matching requirements of a switched capacitor DAC. In comparison to the conventional switched capacitor SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable switched capacitor SAR ADCs. Moreover, low-impedance DAC-reference voltages which are essential for switched capacitor DAC are removed by using this approach. In validating the proposed approach, a prototype 10-bit ADC is fabricated in a 90 nm TSMC CMOS process. Measured results of the ADC show an SFDR of 58.4 dB at 50 MS/s, while consuming 6 mW from a 1.2/1.8 V supply.dc.description.abstract
Languageendc.language.iso
PublisherUniversität Ulmdc.publisher
LicenseStandarddc.rights
Link to license texthttps://oparu.uni-ulm.de/xmlui/license_v3dc.rights.uri
KeywordCurrent mode signal processingdc.subject
Dewey Decimal GroupDDC 004 / Data processing & computer sciencedc.subject.ddc
LCSHSuccessive approximation analog-to-digital convertersdc.subject.lcsh
LCSHSignal processingdc.subject.lcsh
TitleConcept and design of a high speed current mode based SAR ADCdc.title
Resource typeDissertationdc.type
Date of acceptance2016-06-10dcterms.dateAccepted
RefereeOrtmanns, Mauritsdc.contributor.referee
RefereeWicht, Bernharddc.contributor.referee
DOIhttp://dx.doi.org/10.18725/OPARU-4057dc.identifier.doi
PPN864382227dc.identifier.ppn
URNhttp://nbn-resolving.de/urn:nbn:de:bsz:289-oparu-4096-1dc.identifier.urn
GNDAnalog-Digital-Umsetzerdc.subject.gnd
GNDDigitale Signalverarbeitungdc.subject.gnd
FacultyFakultät für Ingenieurwissenschaften, Informatik und Psychologieuulm.affiliationGeneral
InstitutionInstitut für Mikroelektronikuulm.affiliationSpecific
Shelfmark print versionW: W-H 14.792uulm.shelfmark
Grantor of degreeFakultät für Ingenieurwissenschaften, Informatik und Psychologieuulm.thesisGrantor
DCMI TypeTextuulm.typeDCMI
TypeErstveröffentlichunguulm.veroeffentlichung
CategoryPublikationenuulm.category
University Bibliographyjauulm.unibibliographie


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