Automated conversion from LUT-based FPGAs to LUT-based MPGAs
Veredas Ramirez, Francisco Javier
FacultiesFakultät für Ingenieurwissenschaften und Informatik
LicenseStandard (Fassung vom 03.05.2003)
Field-programmable gate-arrays (FPGAs) are used for ASIC prototyping or small volume products. In medium to large volume products, the prototyping design or the small volume product is converted to another IC structure such as mask-programmable gate arrays (MPGAs). MPGAs are of growing importance because of the increase of design cost, and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated FPGA prototype-design into an MPGA. The MPGA design uses potentially less area, delay, and dynamic power consumption than the FPGA design. In this thesis, two new LUT-based MPGAs are presented. The MPGA architectures preserve the logic of an FPGA and have a regular routing interconnect scheme. The use of a regular routing architecture reduces the time for physical verification. The first MPGA presented, r-MPGA, is a direct migration from an FPGA, i.e. the programmable interconnect points (PIPs) and the latches used for logic configuration are substituted by metallization. The second MPGA, Zelix MPGA, has a new routing architecture which only uses two metal layers for mask-programming. The conversion flow for the Zelix MPGA is presented. The conversion flow preserves the gate-level netlist and the re-use of the placement. The re-use of the same gate-level netlist minimizes the time for formal verification. The resulting flow has a special routing tool and buffer insertion algorithm for timing integrity. In addition, a simple methodology to estimate power consumption is presented. Power consumption is estimated using gate-level information. Comparison with transistor-level simulations shows a difference of 4.83 % in the gate-level power consumption estimation. In comparison with an FPGA, the area is reduced by 82 % in the logic and by up-to 64 % in the whole device. To investigate the delay and the power consumption, a set of application circuits has been mapped. Experimental investigations show that the critical path is reduced in average by 48 % compared with the FPGA. The reduction of dynamic power consumption is 72 % on average. Static power consumption on the Zelix MPGA is less than 1 % of the total power consumption. The conversion flow is rather simple and can map a designed circuit within one day.
Subject HeadingsKundenspezifische Schaltung [GND]
Digital design and applications [LCSH]
Field programmable gate arrays [LCSH]