A performance analysis model for a management architecture of multicore processing units
Auch gedruckt in der BibliothekW: W-H 14.708
FakultätFakultät für Ingenieurwissenschaften, Informatik und Psychologie
InstitutionInstitut für Organisation und Management von Informationssystemen
Ressourcen- / MedientypAbschlussarbeit (Master; Diplom), Text
Datum der Erstveröffentlichung2016-05-23
In the field of high performance computing the partitioning of a problem into smaller problems, that then are solved in parallel on multiple computing units, is a crucial task. In current software architectures the solving of those smaller problems on the operating system and application layer is carried out by threads, which have to be created and managed by the operating system. These tasks are computationally expensive. Because of the monolithic kernel of most modern operating systems, the tasks of managing and activating threads are sequentially performed by a central instance and are therefore hard to parallelize. For high performance systems, utilizing a large number of processing units, this centralized processing becomes a bottleneck. Operating system architectures, that are tailored for manycore processors, aim for parallelization and distribution of internal tasks of the kernel. This also applies to the management of threads, for which currently no universal model exists. Although a performance gain can be expected when using a distributed management of threads, additional tasks, like the synchronization of state or the delegation of tasks between the management instances, may impact the performance. In this thesis a generic model for a distributed thread management is developed. The influence of the number of thread management instances on the performance of applications is examined. This model offers a possibility to derive an optimal configuration of management instances in respect of distribution and communication overhead for a specific hardware configuration. This configuration significantly influences the latencies for creation of different amounts of threads, which should be minimized. The developed model is evaluated and validated by deriving a description for a specific hardware configuration. This description is then realized by an appropriate thread management facility which is implemented and integrated within a specialized OS.