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AuthorVogelmann, Patrickdc.contributor.author
AuthorWagner, Johannesdc.contributor.author
AuthorHaas, Michaeldc.contributor.author
AuthorOrtmanns, Mauritsdc.contributor.author
Date of accession2021-05-04T11:36:18Zdc.date.accessioned
Available in OPARU since2021-05-04T11:36:18Zdc.date.available
Date of first publication2019-01-29dc.date.issued
AbstractThis paper presents a dynamic power reduction technique for incremental ΔΣ (I-ΔΣ) modulators. The technique makes use of the unequal weighting of the digital reconstruction filter. The underlying idea is that the input signal samples are not equally weighted in the higher order reconstruction filter. Thus, it is possible to increase the non-idealities of the I-ΔΣ modulator during the runtime of a single Nyquist conversion, thereby saving power. This principal idea is verified by an example design, where the input-referred noise of the first integrator is dynamically increased, which allows for improved efficiency. The proposed technique is readily applicable to every state-of-the-art I-ΔΣ modulator. Furthermore, it is shown that this property can also be used to switch a single-bit digital-to-analog converter (DAC) into a multibit DAC during runtime, thereby greatly improving the achievable signal-to-quantization-noise ratio (SQNR) without suffering from the DAC non-linearity. The prototype I-ΔΣ modulator is manufactured in a 180-nm CMOS technology and achieves a dynamic range/SNDR = 91.5/86.6 dB for a sampling rate of 200 kS/s while consuming l.l mW from a 3-V supply, while the dynamic power reduction method accounts for 30% power savings.dc.description.abstract
Languageen_USdc.language.iso
PublisherUniversität Ulmdc.publisher
LicenseStandarddc.rights
Link to license texthttps://oparu.uni-ulm.de/xmlui/license_v3dc.rights.uri
KeywordAnalog-to-digital converter (ADC)dc.subject
Keywordbiomedicaldc.subject
Keyworddelta–sigmadc.subject
Keyworddiscrete timedc.subject
Keyworddynamic power reductiondc.subject
Keywordslicingdc.subject
Dewey Decimal GroupDDC 620 / Engineering & allied operationsdc.subject.ddc
LCSHAnalog-to-digital convertersdc.subject.lcsh
LCSHDiscrete-time systemsdc.subject.lcsh
TitleA dynamic power reduction technique for incremental delta sigma modulatorsdc.title
Resource typeWissenschaftlicher Artikeldc.type
VersionacceptedVersiondc.description.version
DOIhttp://dx.doi.org/10.18725/OPARU-36941dc.identifier.doi
URNhttp://nbn-resolving.de/urn:nbn:de:bsz:289-oparu-37003-0dc.identifier.urn
GNDBiomedizinische Technikdc.subject.gnd
FacultyFakultät für Ingenieurwissenschaften, Informatik und Psychologieuulm.affiliationGeneral
InstitutionInstitut für Mikroelektronikuulm.affiliationSpecific
Peer reviewjauulm.peerReview
DCMI TypeTextuulm.typeDCMI
CategoryPublikationenuulm.category
DOI of original publication10.1109/JSSC.2019.2892602dc.relation1.doi
Source - Title of sourceIEEE Journal of Solid-State Circuitssource.title
Source - Place of publicationInstitute of Electrical and Electronics Engineerssource.publisher
Source - Volume54source.volume
Source - Issue5source.issue
Source - Year2019source.year
Source - From page1455source.fromPage
Source - To page1467source.toPage
Source - ISSNISSN 0018-9200source.identifier.issn
Source - eISSNeISSN 1558-173Xsource.identifier.eissn
FundingDFG [OR 245/13-1]uulm.funding
Suitable communityFakultät für Ingenieurwissenschaften, Informatik und Psychologieuulm.community
University Bibliographyjauulm.unibibliographie


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