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AuthorSchuster, Markusdc.contributor.author
Date of accession2016-03-15T09:03:59Zdc.date.accessioned
Available in OPARU since2016-03-15T09:03:59Zdc.date.available
Year of creation2013dc.date.created
AbstractPhysical Unclonable Functions (PUFs) present a promising concept for cryptographic hardware. PUFs provide a challenge-response scheme, where the response is not calculated but determined by a kind of randomness available in the device. Every PUF behaves different, even equally manufactured ones. The Arbiter PUF makes use of race conditions between equally designed delay paths. Although the basic principle is proven to work, it suffers from predictability attacks and a not negligible quantity of unreproducible response bits. This thesis deals with the simulation and enhancement of Arbiter PUFs in CMOS technology. A novel simulation approach is introduced, which allows a reliable prediction of the Arbiter PUF"s reproducibility behavior without a transistor level simulation of the whole system. Only the components need to be characterized by circuit simulations using industrial manufacturer models. The resulting PUF can be modeled on a higher level and simulated very fast using statistical distributions. Furthermore the influence of some design parameters on each component"s characteristic is investigated. An enhanced parameter set is determined and evaluated using the new simulation approach. Finally the results are verified by transient transistor level simulations for the reference and the enhanced Arbiter PUF. The bit error rate could be reduced by 61 percent just by design parameter modifications of specific transistors.dc.description.abstract
Languageendc.language.iso
PublisherUniversität Ulmdc.publisher
LicenseStandarddc.rights
Link to license texthttps://oparu.uni-ulm.de/xmlui/license_v3dc.rights.uri
KeywordArbiter PUFdc.subject
KeywordDelay-based PUFdc.subject
KeywordHardware securitydc.subject
KeywordPhysical unclonable functiondc.subject
KeywordPUFdc.subject
Dewey Decimal GroupDDC 004 / Data processing & computer sciencedc.subject.ddc
LCSHAuthenticationdc.subject.lcsh
LCSHComputer securitydc.subject.lcsh
LCSHCryptographydc.subject.lcsh
LCSHData protectiondc.subject.lcsh
LCSHIntegrated circuitsdc.subject.lcsh
TitleEnhanced physical unclonable function structures in mixed-signal MOS technologydc.title
Resource typeAbschlussarbeit (Master; Diplom)dc.type
DOIhttp://dx.doi.org/10.18725/OPARU-2525dc.identifier.doi
PPN781326249dc.identifier.ppn
URNhttp://nbn-resolving.de/urn:nbn:de:bsz:289-vts-88605dc.identifier.urn
GNDCMOSdc.subject.gnd
GNDKryptologiedc.subject.gnd
GNDKundenspezifische Schaltungdc.subject.gnd
GNDMOSdc.subject.gnd
GNDSimulationdc.subject.gnd
FacultyFakultät für Ingenieurwissenschaften und Informatikuulm.affiliationGeneral
Date of activation2014-03-14T10:34:53Zuulm.freischaltungVTS
Peer reviewneinuulm.peerReview
DCMI TypeTextuulm.typeDCMI
VTS-ID8860uulm.vtsID
CategoryPublikationenuulm.category
University Bibliographyjauulm.unibibliographie


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