A 64 to 81 GHz PLL with low phase noise in an 80 GHz SiGe HBT technology

Abstract

This paper presents a 64 to 81 GHz PLL realized in a low-cost, 80 GHz HBT technology. The circuit consists of a wide tuning range VCO, a push-push frequency doubler and an analog PLL (divide by 32 frequency divider, phase detector and active loop filter) for phase locking. The measured phase noise is - 106 dB/Hz at 1 MHz offset. Output power is - 2.5 dBm at 64 GHz and slowly decreases to - 6 dBm at 81 GHz. DC power consumption is 431 mW. The circuit achieves the widest frequency tuning range and lowest phase noise among the reported PLLs in a similar frequency range.