A 64 to 81 GHz PLL with low phase noise in an 80 GHz SiGe HBT technology

peer-reviewed
Veröffentlichung
2013-03-26Authors
Liu, Gang
Trasser, Andreas
Schumacher, Hermann
Beitrag zu einer Konferenz
Faculties
Fakultät für Ingenieurwissenschaften und InformatikConference
IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2012-01-16 - 2012-01-18, Santa Clara, CA
Abstract
This paper presents a 64 to 81 GHz PLL realized in a low-cost, 80 GHz HBT technology. The circuit consists of a wide tuning range VCO, a push-push frequency doubler and an analog PLL (divide by 32 frequency divider, phase detector and active loop filter) for phase locking. The measured phase noise is - 106 dB/Hz at 1 MHz offset. Output power is - 2.5 dBm at 64 GHz and slowly decreases to - 6 dBm at 81 GHz. DC power consumption is 431 mW. The circuit achieves the widest frequency tuning range and lowest phase noise among the reported PLLs in a similar frequency range.
Date created
2012
Original publication
2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 16-18 January 2012 Santa Clara, CA, USA, S. 171 - 174http://dx.doi.org/10.1109/SiRF.2012.6160133
Subject headings
[GND]: Heterobipolartransistor | VCO[LCSH]: Phase-locked loops | Voltage-controlled oscillators
[Free subject headings]: Heterojunction-bipolar-transistors
[DDC subject group]: DDC 620 / Engineering & allied operations
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Please use this identifier to cite or link to this item: http://dx.doi.org/10.18725/OPARU-2472
Liu, Gang; Trasser, Andreas; Schumacher, Hermann (2013): A 64 to 81 GHz PLL with low phase noise in an 80 GHz SiGe HBT technology. Open Access Repositorium der Universität Ulm und Technischen Hochschule Ulm. http://dx.doi.org/10.18725/OPARU-2472
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