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A 64-84-GHz PLL with low phase noise in an 80 GHz SiGe HBT technology

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11 S.

peer-reviewed

Veröffentlichung
2013-01-31
Authors
Liu, Gang
Trasser, Andreas
Schumacher, Hermann
Wissenschaftlicher Artikel


Faculties
Fakultät für Ingenieurwissenschaften und Informatik
Abstract
This paper presents a 64-84 GHz phase-locked loop (PLL) realized in a low-cost 80-GHz HBT technology. The circuit consists of a wide tuning-range voltage-controlled oscillator, a push-push frequency doubler, a divide-by-32 frequency divider, a phase detector and an active loop filter. The measured phase noise at 1 MHz offset is -106 dBc/Hz. The output power is -2.5 dBm at 64 GHz, and it slowly decreases to -8.1 dBm at 84 GHz, with a maximum dc power consumption of 517 mW. To the authors’ knowledge, the circuit achieves the widest frequency tuning range and its in-band phase noise is the lowest among the fully integrated V/W-band PLLs reported to date.
Date created
2012
Original publication
IEEE transactions on microwave theory and techniques 60 (2012), S. 3739 - 3748
https://doi.org/10.1109/TMTT.2012.2213833
Subject headings
[GND]: Heterobipolartransistor | Phasenregelkreis
[LCSH]: Phase-locked loops
[Free subject headings]: Heterojunction bipolar transistors (HBTs) | Millimeter-wave (mm-wave) integrated circuits (ICs) | PLLs
[DDC subject group]: DDC 620 / Engineering & allied operations
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https://oparu.uni-ulm.de/xmlui/license_v3

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DOI & citation

Please use this identifier to cite or link to this item: http://dx.doi.org/10.18725/OPARU-2461

Liu, Gang; Trasser, Andreas; Schumacher, Hermann (2013): A 64-84-GHz PLL with low phase noise in an 80 GHz SiGe HBT technology. Open Access Repositorium der Universität Ulm und Technischen Hochschule Ulm. http://dx.doi.org/10.18725/OPARU-2461
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