A 64-84-GHz PLL with low phase noise in an 80 GHz SiGe HBT technology
FacultiesFakultät für Ingenieurwissenschaften und Informatik
This paper presents a 64-84 GHz phase-locked loop (PLL) realized in a low-cost 80-GHz HBT technology. The circuit consists of a wide tuning-range voltage-controlled oscillator, a push-push frequency doubler, a divide-by-32 frequency divider, a phase detector and an active loop filter. The measured phase noise at 1 MHz offset is -106 dBc/Hz. The output power is -2.5 dBm at 64 GHz, and it slowly decreases to -8.1 dBm at 84 GHz, with a maximum dc power consumption of 517 mW. To the authors’ knowledge, the circuit achieves the widest frequency tuning range and its in-band phase noise is the lowest among the fully integrated V/W-band PLLs reported to date.
Original publicationIEEE transactions on microwave theory and techniques 60 (2012), S. 3739 - 3748
Digital Object Identifier 10.1109/TMTT.2012.2213833
Subject HeadingsHeterobipolartransistor [GND]
Phase-locked loops [LCSH]