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AuthorMandry, Holgerdc.contributor.author
AuthorHerkle, Andreasdc.contributor.author
AuthorKürzinger, Ludwigdc.contributor.author
AuthorMüelich, Svendc.contributor.author
AuthorBecker, Joachimdc.contributor.author
AuthorFischer, Robertdc.contributor.author
AuthorOrtmanns, Mauritsdc.contributor.author
Date of accession2019-08-28T10:20:09Zdc.date.accessioned
Available in OPARU since2019-08-28T10:20:09Zdc.date.available
Date of first publication2019-05-01dc.date.issued
AbstractPhysical Unclonable Functions (PUFs) offer the possibility to produce unique fingerprints for integrated circuits. As raw PUF responses are affected by noise, some post-processing steps are necessary. We present a coding chain test framework for PUFs on Field Programmable Gate Arrays. The framework allows easy exchange, evaluation and comparison of different PUF implementations, coding algorithms and other chain modules. For a testing framework, the execution time of the evaluated algorithm is a bottleneck, since a huge amount of runs are supposed to be done. Hence, we additionally present a new type of Reed-Muller decoder hardware architecture using parallel modules to speed up the decoding process. The decoding time could be decreased by 95% in comparison to existing implementations at the cost of 41 times higher slice count.dc.description.abstract
Languageen_USdc.language.iso
PublisherUniversität Ulmdc.publisher
LicenseStandard (ohne Print-on-Demand)dc.rights
Link to license texthttps://oparu.uni-ulm.de/xmlui/license_opod_v1dc.rights.uri
KeywordReed-Mullerdc.subject
KeywordPUFdc.subject
KeywordPhysical unclonable functiondc.subject
KeywordField programmable gate arraydc.subject
KeywordGeneralized concatenated codesdc.subject
Dewey Decimal GroupDDC 004 / Data processing & computer sciencedc.subject.ddc
Dewey Decimal GroupDDC 620 / Engineering & allied operationsdc.subject.ddc
LCSHField programmable gate arrays ; Congressesdc.subject.lcsh
LCSHIntegrated circuitsdc.subject.lcsh
LCSHComputer engineering ; Congressesdc.subject.lcsh
MeSHTransistors, Electronicdc.subject.mesh
TitleModular PUF coding chain with high-speed Reed-Muller decoderdc.title
Resource typeBeitrag zu einer Konferenzdc.type
VersionacceptedVersiondc.description.version
DOIhttp://dx.doi.org/10.18725/OPARU-18293dc.identifier.doi
PPN1678631175dc.identifier.ppn
URNhttp://nbn-resolving.de/urn:nbn:de:bsz:289-oparu-18350-3dc.identifier.urn
GNDRM-Codedc.subject.gnd
GNDKonkatenationscodedc.subject.gnd
GNDIntegrierte Schaltungdc.subject.gnd
FacultyFakultät für Ingenieurwissenschaften, Informatik und Psychologieuulm.affiliationGeneral
InstitutionInstitut für Mikroelektronikuulm.affiliationSpecific
InstitutionInstitut für Nachrichtentechnikuulm.affiliationSpecific
Peer reviewjauulm.peerReview
DCMI TypeTextuulm.typeDCMI
CategoryPublikationenuulm.category
In cooperation withTechnische Universität Münchenuulm.cooperation
DOI of original publication10.1109/ISCAS.2019.8702484dc.relation1.doi
Source - Title of source2019 IEEE International Symposium on Circuits and Systems (ISCAS)source.title
Quellenangabe - HerausgeberInstitute of Electrical and Electronics Engineerssource.contributor.editor1
Source - Place of publicationIEEEsource.publisher
Source - Year2019source.year
Source - ISSN2158-1525source.identifier.issn
Source - ISBN978-1-7281-0397-6source.identifier.isbn
FundingMehrwertige Physikalisch Unklonbare Funktionen / DFG [401330297, FI 982/15-1]uulm.funding
Conference nameISCAS 2019 - IEEE International Symposium on Circuits and Systemsuulm.conferenceName
Conference placeSapporouulm.conferencePlace
Conference start date2019-05-26uulm.conferenceStartDate
Conference end date2019-05-29uulm.conferenceEndDate
Bibliographyuulmuulm.bibliographie


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