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AuthorBeuschel, Christianedc.contributor.author
Date of accession2016-03-15T06:22:55Zdc.date.accessioned
Available in OPARU since2016-03-15T06:22:55Zdc.date.available
Year of creation2010dc.date.created
AbstractIn recent years, the amount of digital data which is stored and transmitted for private and public usage has increased considerably. To allow a save transmission and storage of data despite of error-prone transmission media, error correcting codes are used. A large variety of codes has been developed, and in the past decade low-density parity-check (LDPC) codes which have an excellent error correction performance became more and more popular. Today, low-density parity-check codes have been adopted for several standards, and efficient decoder hardware architectures are known for the chosen structured codes. However, the existing decoder designs lack flexibility as only few structured codes can be decoded with one decoder chip. In consequence, different codes require a redesign of the decoder, and few solutions exist for decoding of codes which are not quasi-cyclic or which are unstructured. In this thesis, three different approaches are presented for the implementation of fully programmable LDPC decoders which can decode arbitrary LDPC codes. As a design study, the first programmable decoder which uses a heuristic mapping algorithm is realized on a field-programmable gate array (FPGA), and error correction curves are measured to verify the correct functionality. The main contribution of this thesis lies in the development of the second and the third architecture and an appropriate mapping algorithm. The proposed fully programmable decoder architectures use one-phase message passing and layered decoding and can decode arbitrary LDPC codes using an optimum mapping and scheduling algorithm. The presented programmable architectures are in fact generalized decoder architectures from which the known decoder architectures for structured LDPC codes can be derived.dc.description.abstract
Languageendc.language.iso
PublisherUniversität Ulmdc.publisher
LicenseStandard (Fassung vom 01.10.2008)dc.rights
Link to license texthttps://oparu.uni-ulm.de/xmlui/license_v2dc.rights.uri
KeywordLayered decodingdc.subject
KeywordLDPCdc.subject
KeywordLow-density parity-checkdc.subject
KeywordProgrammable decoder architecturedc.subject
Dewey Decimal GroupDDC 004 / Data processing & computer sciencedc.subject.ddc
LCSHError-correcting codes: Information theorydc.subject.lcsh
LCSHGraph coloringdc.subject.lcsh
TitleFully programmable LDPC decoder hardware architecturesdc.title
Resource typeDissertationdc.type
DOIhttp://dx.doi.org/10.18725/OPARU-1737dc.identifier.doi
PPN640751555dc.identifier.ppn
URNhttp://nbn-resolving.de/urn:nbn:de:bsz:289-vts-74244dc.identifier.urn
GNDDecodierungdc.subject.gnd
GNDFehlerkorrekturcodedc.subject.gnd
GNDLow-Density-Parity-Check-Codedc.subject.gnd
FacultyFakultät für Ingenieurwissenschaften und Informatikuulm.affiliationGeneral
Date of activation2010-11-16T07:35:55Zuulm.freischaltungVTS
Peer reviewneinuulm.peerReview
Shelfmark print versionZ: J-H 13.837; W: W-H 12.305uulm.shelfmark
DCMI TypeTextuulm.typeDCMI
VTS-ID7424uulm.vtsID
CategoryPublikationenuulm.category
University Bibliographyjauulm.unibibliographie


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