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Fully programmable LDPC decoder hardware architectures

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vts_7424_10550.pdf (1.644Mb)
171 Seiten
 
Veröffentlichung
2010-11-16
DOI
10.18725/OPARU-1737
Dissertation


Authors
Beuschel, Christiane
Faculties
Fakultät für Ingenieurwissenschaften und Informatik
License
Standard (Fassung vom 01.10.2008)
https://oparu.uni-ulm.de/xmlui/license_v2
Abstract
In recent years, the amount of digital data which is stored and transmitted for private and public usage has increased considerably. To allow a save transmission and storage of data despite of error-prone transmission media, error correcting codes are used. A large variety of codes has been developed, and in the past decade low-density parity-check (LDPC) codes which have an excellent error correction performance became more and more popular. Today, low-density parity-check codes have been adopted for several standards, and efficient decoder hardware architectures are known for the chosen structured codes. However, the existing decoder designs lack flexibility as only few structured codes can be decoded with one decoder chip. In consequence, different codes require a redesign of the decoder, and few solutions exist for decoding of codes which are not quasi-cyclic or which are unstructured. In this thesis, three different approaches are presented for the implementation of fully programmable LDPC decoders which can decode arbitrary LDPC codes. As a design study, the first programmable decoder which uses a heuristic mapping algorithm is realized on a field-programmable gate array (FPGA), and error correction curves are measured to verify the correct functionality. The main contribution of this thesis lies in the development of the second and the third architecture and an appropriate mapping algorithm. The proposed fully programmable decoder architectures use one-phase message passing and layered decoding and can decode arbitrary LDPC codes using an optimum mapping and scheduling algorithm. The presented programmable architectures are in fact generalized decoder architectures from which the known decoder architectures for structured LDPC codes can be derived.
Date created
2010
Subject Headings
Decodierung [GND]
Fehlerkorrekturcode [GND]
Low-Density-Parity-Check-Code [GND]
Error-correcting codes: Information theory [LCSH]
Graph coloring [LCSH]
Keywords
Layered decoding; LDPC; Low-density parity-check; Programmable decoder architecture
Dewey Decimal Group
DDC 004 / Data processing & computer science

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Beuschel, Christiane (2010): Fully programmable LDPC decoder hardware architectures. Open Access Repositorium der Universität Ulm. Dissertation. http://dx.doi.org/10.18725/OPARU-1737

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