3-dimensional chip integration: technology and critical issues
FakultätenFakultät für Ingenieurwissenschaften und Informatik
LizenzStandard (Fassung vom 01.10.2008)
The increasing integration density in monolithic circuit fabrication leads to a wiring problem. A solution offers the use of 3-dimensional chip integration with through chip vias. In this case, several highly interconnected chip layers sharing one base substrate by stacking them on top of each other. This enables very short electrical connections with small parasitics. This work describes one approach for a successful 3D integration method. The chip stacking technology discussed enables the massively parallel communication between two chip layers. The maximum interconnect density lies at 4400 vias/mm² with interconnects shorter than 20 µm. This high density opens various application areas like neural networks, densely cross-linked processors or image detection with integrated signal procesing. A critical issue of this integration technology is the via isolation. By using different isolation methods, the leakage of one via lies below 200 pA per via. Another aspect in this work is the complete thermal behavior of a chip stack during process and in operation. FEM simulations show some limitations and critical spots in the stack in terms of temperature and thermal mechanical stress.
Erstellung / Fertigstellung
Normierte SchlagwörterChip [GND]
Dreidimensionale Integration [GND]
Via: Electricity [LCSH]