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AuthorAlMarashli, Ahmaddc.contributor.author
Date of accession2019-06-11T12:46:24Zdc.date.accessioned
Available in OPARU since2019-06-11T12:46:24Zdc.date.available
Year of creation2018dc.date.created
Date of first publication2019-06-11dc.date.issued
AbstractSAR ADCs recorded the highest power efficiency in the last decade, while employing a simple architecture and making a perfect use of the advanced digital capabilities in modern deeply-scaled CMOS technologies. Recently, there is an increased importance of high-resolution high-linearity Nyquist-rate ADCs with multiplexing capabilities, in areas like environmental and medical applications. Simultaneously, high power efficiency and low-area consumption are essential features to enable efficient implementations in battery-powered and/or hand-held devices. The state-of-the-art for high-linearity ADCs is dominated by oversampling ADCs, which do not allow multiplexing. On the other hand, available high-linearity Nyquist-rate ADCs require high-power and large chip area for matching enhancement, linearization and calibration techniques. Additionally, these ADCs prefer older technologies for advantageous analog processing. Also, highly-efficient SAR ADCs currently present limited linearity and resolution. This work aims to introduce novel concepts for SAR ADCs, which enable high-linearity A/D conversion with reliance neither on extensive digital linearization nor on large chip area. Instead, the proposed concept makes use of an intrinsically linear Sigma Delta DAC, to enhance the linearity of the SAR ADC. To implement this proposal, two system architectures are introduced and compared to available solutions in the state-of-the-art. Also, system-level design choices are discussed with pros and cons. A prototype in a 40 nm CMOS technology was implemented and measured to validate the proposed technique. The measured linearity of the prototype competes the state-of-the-art for high-linearity power-efficient Nyquist-rate ADCs, while occupying the smallest active chip area, with good stability over PVT variations. The proposed concept, with silicon-validated performance, advances the state-of-the-art for high-linearity, scaling-friendly, simple and power-efficient Nyquist-rate ADCs.dc.description.abstract
Languageen_USdc.language.iso
PublisherUniversität Ulmdc.publisher
LicenseStandarddc.rights
Link to license texthttps://oparu.uni-ulm.de/xmlui/license_v3dc.rights.uri
KeywordSAR ADCdc.subject
KeywordSigma deltadc.subject
KeywordNyquist ADCdc.subject
KeywordHigh resolutiondc.subject
KeywordSelf calibrationdc.subject
KeywordHigh resolution DACdc.subject
KeywordSD DACdc.subject
KeywordOversamplingdc.subject
KeywordHigh SFDRdc.subject
Dewey Decimal GroupDDC 620 / Engineering & allied operationsdc.subject.ddc
LCSHRedundancy (Engineering)dc.subject.lcsh
LCSHCalibrationdc.subject.lcsh
LCSHSuccessive approximation analog-to-digital convertersdc.subject.lcsh
TitleHigh linearity Sigma-Delta-enhanced SAR ADCsdc.title
Resource typeDissertationdc.type
Date of acceptance2019-03-05dcterms.dateAccepted
RefereeOrtmanns, Mauritsdc.contributor.referee
DOIhttp://dx.doi.org/10.18725/OPARU-15015dc.identifier.doi
PPN1667544667dc.identifier.ppn
URNhttp://nbn-resolving.de/urn:nbn:de:bsz:289-oparu-15072-2dc.identifier.urn
GNDSigma-Delta-Wandlerdc.subject.gnd
GNDKalibrieren <Messtechnik>dc.subject.gnd
FacultyFakultät für Ingenieurwissenschaften, Informatik und Psychologieuulm.affiliationGeneral
InstitutionInstitut für Mikroelektronikuulm.affiliationSpecific
Grantor of degreeFakultät für Ingenieurwissenschaften, Informatik und Psychologieuulm.thesisGrantor
DCMI TypeTextuulm.typeDCMI
CategoryPublikationenuulm.category
Bibliographyuulmuulm.bibliographie


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