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Measurement data of the publication: "In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs"

old_ro_csv.zip (533.6Mb)
old_ro_mat.zip (599.6Mb)
new_ro_csv.zip (533.0Mb)
new_ro_mat.zip (598.5Mb)
new_ro_carry4_csv.zi ... (544.4Mb)
new_ro_carry4_mat.zi ... (640.9Mb)
README.md (4.042Kb)
Erstveröffentlichung
2019-05-14
Data creator
Herkle, Andreas
Becker, Joachim
Ortmanns, Maurits
Mandry, Holger
Forschungsdaten


Faculties
Fakultät für Ingenieurwissenschaften, Informatik und Psychologie
Institutions
Institut für Mikroelektronik
Conference
IEEE International Symposium on Hardware Oriented Security and Trust (HOST) - 2019, 2019-05-06 - 2019-05-10, Tyson Corner, USA
Abstract
The presented measurement data is the base of the publication "In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs" presented on May 9th, 2019 at IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2019. The measurement data is presented in two formats, as comma-separated values (.csv) and as native matlab files (.mat). Three different data sets are provided with different hardware settings, as discussed in the publication: old-ro, new-ro and carry-4. Therefore, 6 different files are available.
Date created
2018
Is supplement to
https://doi.org/10.1109/HST.2019.8740832
http://dx.doi.org/10.18725/OPARU-17952
Subject headings
[GND]: Hardware
[LCSH]: Computer engineering | Field programmable gate arrays; Design and construction | Hardware; Tables
[Free subject headings]: Field programmable gate array
[DDC subject group]: DDC 620 / Engineering & allied operations
License
CC BY 4.0 International
http://creativecommons.org/licenses/by/4.0/

Metadata
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DOI & citation

Please use this identifier to cite or link to this item: http://dx.doi.org/10.18725/OPARU-14107

Herkle, Andreas et al. (2019): Measurement data of the publication: "In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs". Open Access Repositorium der Universität Ulm und Technischen Hochschule Ulm. http://dx.doi.org/10.18725/OPARU-14107
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