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AuthorKirchmayr, Matthiasdc.contributor.author
Date of accession2016-03-14T15:20:09Zdc.date.accessioned
Available in OPARU since2016-03-14T15:20:09Zdc.date.available
Year of creation2009dc.date.created
AbstractFuture innovations in the motorring industry will be coined considerably by interlaced E/E components. In this connection the test of these components plays a crucial role. Usually so-called hardware-in-the-loop (HIL) test systems are used for this task. These offer the possibility of running tests automated and reproducible under real time conditions. Already today time is the limiting factor for test activities, last but not least because of the still shortening development cycles of the controllers. The increasing complexity of future systems will continue to intensify this situation. The procedure developed in this work can make a contribution for more efficient utilization of time and thus ease the conflict between complex, high-quality products and a shortened development time. The idea of this procedure insists in the simultaneous execution of several test routines on the same test system. For this it must be clarified beforehand whether the programs affect each other mutually and thus inadvertent reciprocal effects exist. This work presents criteria to recognize independent test routines automatically and to execute them in parallel on the same test system. A procedure maximizing the saving of time guarantees the optimal combination of test routines thereby.dc.description.abstract
Languagededc.language.iso
PublisherUniversität Ulmdc.publisher
LicenseStandard (Fassung vom 01.10.2008)dc.rights
Link to license texthttps://oparu.uni-ulm.de/xmlui/license_v2dc.rights.uri
KeywordE/E-Testsdc.subject
KeywordParallelisierung von Testsdc.subject
KeywordSystemintegrationstestdc.subject
Dewey Decimal GroupDDC 004 / Data processing & computer sciencedc.subject.ddc
LCSHSystems integration. Testingdc.subject.lcsh
TitleZur Parallelisierung von Systemintegrationstests im E/E Umfelddc.title
Resource typeDissertationdc.type
DOIhttp://dx.doi.org/10.18725/OPARU-1091dc.identifier.doi
PPN602674913dc.identifier.ppn
URNhttp://nbn-resolving.de/urn:nbn:de:bsz:289-vts-68698dc.identifier.urn
GNDHardware-in-the-loopdc.subject.gnd
GNDSystemintegrationdc.subject.gnd
FacultyFakultät für Mathematik und Wirtschaftswissenschaftenuulm.affiliationGeneral
Date of activation2009-06-21T23:01:34Zuulm.freischaltungVTS
Peer reviewneinuulm.peerReview
Shelfmark print versionZ: J-H 13.305; N: J-H 9.861uulm.shelfmark
DCMI TypeTextuulm.typeDCMI
VTS ID6869uulm.vtsID
CategoryPublikationenuulm.category
Bibliographyuulmuulm.bibliographie


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