Zur Parallelisierung von Systemintegrationstests im E/E Umfeld
Auch gedruckt in der BibliothekZ: J-H 13.305; N: J-H 9.861
FakultätenFakultät für Mathematik und Wirtschaftswissenschaften
LizenzStandard (Fassung vom 01.10.2008)
Future innovations in the motorring industry will be coined considerably by interlaced E/E components. In this connection the test of these components plays a crucial role. Usually so-called hardware-in-the-loop (HIL) test systems are used for this task. These offer the possibility of running tests automated and reproducible under real time conditions. Already today time is the limiting factor for test activities, last but not least because of the still shortening development cycles of the controllers. The increasing complexity of future systems will continue to intensify this situation. The procedure developed in this work can make a contribution for more efficient utilization of time and thus ease the conflict between complex, high-quality products and a shortened development time. The idea of this procedure insists in the simultaneous execution of several test routines on the same test system. For this it must be clarified beforehand whether the programs affect each other mutually and thus inadvertent reciprocal effects exist. This work presents criteria to recognize independent test routines automatically and to execute them in parallel on the same test system. A procedure maximizing the saving of time guarantees the optimal combination of test routines thereby.
Erstellung / Fertigstellung
Normierte SchlagwörterHardware-in-the-loop [GND]
Systems integration. Testing [LCSH]